IEEE

An 8-bit 600-MS/s Three-Comparator SAR ADC With MUX-delay Exclusion and LSB Averaging

Abstract: An 8-bit 600-MS/s three-comparator SAR ADC is presented that addresses the MUX-induced delay penalty associated with background comparator-swapping calibration. A MUX-delay exclusion ...
IEEE

An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration

Abstract: This letter presents an 8-bit 400 MS/s 1-then-2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) employing a comparator rotation-based background offset ...